Date: 03/21/2025
About this Forum:
Participants were guided through various coding exercises, focusing on caching, schematic creation, and component manipulation, and the process of correcting errors from the DRC was explained. The importance of creating custom components and rules for fabrication was emphasized, and the process design kit and its components were discussed, along with the importance of a schematic in the design process.
The Rodgers RLE Forum is a time to appreciate and learn from examples of impactful engineering. The laboratory hosts these opportunities for engagement in support of its mission to serve as a cutting-edge hub for advancing and sharing knowledge and best practices in high-performance prototyping.
About the presenters:

Joaquin Matres is a seasoned chip designer with 15 years of experience developing advanced silicon solutions at Intel, Hewlett Packard Labs, PsiQuantum, and Google X. Passionate about leveraging Python for chip design, he founded gdsfactory in 2019—an open-source platform that has transformed chip production workflows, with over 2 million downloads to date.
He collaborates with Google’s Build Your Own Silicon program, working to establish an open-source chip design ecosystem similar to TensorFlow’s impact in machine learning. Committed to innovation and accessibility in silicon design, he strives to push the boundaries of technology while fostering a collaborative, open environment for the next generation of chip designers.
To support enterprise adoption, he also founded GDSFactory+, providing industry-level support for GDSFactory, including foundry PDK access, schematic capture, simulations, and verification (DRC, LVS). To learn more visit GDSFactory.com
